The present invention relates in general to the integrity and reliability of semiconductor chip interconnections, more specifically to the design of multi-layer wiring structures for relieving thermal stresses on solder ball interconnections.
The following three U. S. Patents relate to the design of semiconductor devices with thermal stress relief.
U.S. Pat. No. 5,943,597 dated Aug. 24, 1999, issued to J. H. Kleffner et. al. shows a design for providing stress relief to a solder bumped semiconductor chip by forming a trench that surrounds the individual solder bumps.
U.S. Pat. No. 6,028,364 dated Feb. 22, 2000, issued to M. Ogino et. al. describes a design utilizing an elastomer for thermal stress relief on a bumped semiconductor chip.
U.S. Pat. No. 6,394,819 B1 dated May 28, 2002, issued to B. H. Mosser, III et. al. discloses a design where a dielectric member is used between electrical components to absorb thermal stresses.
The advent of VLSI technology in the semiconductor field has resulted in the demand for high density packaging. Semiconductor packaging traditionally has three levels of package. The first level, a single chip module is made up of a semiconductor chip attached to a substrate that includes interconnections to the next level of package. The substrate and chip assembly is usually molded in an encapsulant for environmental protection. The second level of package, usually a printed circuit card mounts and interconnects the single chip modules and has a connector system to the third level package, usually a planar printed circuit board.
The utilization of VLSI semiconductor chips in commercial electronic products such as cameras, camcorders, DVD players, etc., has demanded that semiconductor packages be highly reliable and space efficient in their designs. In addition military applications require lightweight, space efficient, highly reliable packaging structures.
Elimination of a level of package has been a driving force in electronic system design in the recent past. This reduction in packaging level would allow for closer spacing of semiconductor chips thereby reducing signal delay times. In addition the reduction of a level of package would increase product reliability and decrease product costs. One design currently in use is direct chip attach. In this design chips are flip chip mounted onto a substrate, usually ceramic, and the assembly sealed in an enclosure for environmental protection. The environmental protection is required to protect the semiconductor and the interconnections against corrosive elements and mechanical disturbances. The inclusion of enclosures for environmental protection results in larger packages with longer distances between semiconductor chips and thereby longer signal delays.
In addition, advances in VLSI technology in the semiconductor field has created the need for higher interconnection density on the surface of the semiconductor chip. These interconnections are used to connect the chip terminals to the next level of package or printed circuit board. The need for higher density interconnections results from the smaller circuit devices fabricated by the recent manufacturing advances. The smaller circuits in turn result in higher circuit counts per chip. The higher circuit count requires more signal input, and signal output connections; in addition the higher circuit count requires more power to be delivered to the chip requiring more power connections. This need for higher interconnection density has resulted in interconnection techniques such as solder bumps that are capable of utilizing the total area of the chip thus providing more interconnections per chip.
The reliability of solder bump interconnects in chip scale packaging that utilizes solder ball interconnections and epoxy printed circuit technology for the next level of package, needs to address the problem of thermally induced mechanical stresses. The mechanical stresses in the solder bump result from mechanical strains induced by the difference in the thermal coefficient of expansion (TCE) of the basic materials used, and the temperature changes the packages are exposed to during product use.
In the application where the product utilizes a silicon semiconductor chip and the next level of package is an epoxyxe2x80x94glass printed circuit card and the product usage is in a home or office environment, the resultant thermally induced strains are such that the solder of the solder bumps is stressed beyond the elastic limit of the material. In the plastic range of ductile materials such as solder fatigue cracks develop due to the onxe2x80x94off thermal cycles during product usage. These fatigue cracks are a reliability concern as they eventually result in faulty interconnections.
In order to the thermal stresses on the solder ball interconnections a method currently in use is shown in FIG. 1 (prior art) The semiconductor chip 10 with circuits has a interconnecting wiring structure 12 fabricated by conventional photolithography as shown. The wiring structure 12 is composed of copper Cu or aluminum Al metallurgy and a low expansion polyimide for the insulator. A buffer layer 14 is added to the above structure by soldering or pressure metal bonding the interconnections. Solder balls are added by plating or evaporation. The buffer layer composed low modulus elastomer with thru metal vias for interconnections, provides the stress relief required when the chip scale package is interconnected to the next level package.
The drawbacks to this method of utilizing chip scale packaging directly mounted on printed circuit boards is the additional processes required to add the buffer layer, and the additional electrical delay.
Accordingly it is an object of one or more embodiments of the present invention to provide a multi-layer wiring structure on a semiconductor chip that has the ability to reduce or eliminate the thermally induced mechanical stresses on the solder ball terminals.
It is a further object of one or more embodiments of the present invention that the reduction of the thermal stresses allows for the use of the chip scale package to be directly mounted to a printed circuit interconnect.
Another object of the present invention is that the structure design utilize materials and fabrication processes currently used in semiconductor manufacture.
It is a further object of the present invention that the semiconductor chip with the thermal compliant multi-layered wiring structure can be used in high thermal cycled products with resultant high reliability.
The above objectives are achieved by one or more embodiments of the present invention by providing a multi-layered wiring structure on a semiconductor chip that utilizes interconnect metallurgy and solder balls that are not directly in contact with the supporting dielectric material. The xe2x80x9cemptyxe2x80x9d or air gap under the interconnect metallurgy and solder balls results in a compliant structure that does not transmit thermally induced stresses to the solder ball.
An embodiment of the present invention shown in FIG. 2 wherein the cross-sectional view shows a typical solder ball multi-layer wiring structure fabricated on a semiconductor wafer 20. The semiconductor wafer 20 has a dielectric layer 22, a passivation layer 24, and interconnecting metal pads 26, fabricated on its surface. A metal wiring line 28 is fabricated in a method that allows the metal line 28 not to be in contact with any material on the semiconductor wafer. A solder ball 30 is then fabricated at the end of the wiring line 28. The resultant structure with the xe2x80x9cemptyxe2x80x9d or air gap 32 is totally compliant and does not transmit any thermally induced stresses to the solder ball.
A second, third, fourth, and fifth embodiment of the present invention is shown in FIGS. 3, 4, 5, and 6 respectively. In these embodiments the xe2x80x9cemptyxe2x80x9d or air gap under the wiring line is enclosed on two sides and varies in size, location and shape to allow for different design applications.
The sixth embodiment of the present invention is shown in FIG. 7 and in FIG. 8. In FIG. 7 a cross section of the interconnect metallurgy is shown composed of 5 um thick copper Cu 36 and 5 um thick nickel Ni 34. The top view of the interconnect metallurgy is shown in FIG. 8. This configuration has an xe2x80x9cemptyxe2x80x9d or air gap in the copper line 36 under the solder ball 30 and it provides the required compliance for relieving thermally induced stresses.